Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors

Computationally efficient implementation of sarse-tap FIR adaptive filters with tap-position control on intel IA-32 processors

フォーマット:

論文

責任表示:

Hirano, Akihiro ; Nakayama, Kenji

言語:

英語

出版情報:

IEEE = Institute of Electrical and Electronics Engineers, 2008-01-01

著者名:

掲載情報:

The International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2008)

開始ページ:

292

終了ページ:

295

バージョン:

publisher

概要:

金沢大学理工研究域　電子情報学系<br />This paper presents an computationally ef cient implementation of sparse-tap FIR adaptive lters with tapposition control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order … to overcome randomorder memory access which prevents a ectorization, a blockbased processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66percent speedup is achieved.<br />Organized by the Electrical Engineering/Electronics, Computer, Telecommunications, and Information Technology Association (ECTI) Co-organized by GCEO-NGIT, Hokkaido University Technical sponsored by IEEE Circuits and Systems Society In cooperation with the Institute of Electronics, Information and Communication Engineering (IEICE) 続きを見る

URL:

http://hdl.handle.net/2297/19407

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詳細

受理日:	2008-01-01

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