※一部利用できない機能があります
| 1.
論文 |
論文
|
Nakata, Shunji ; Suzuki, Hirotsugu ; Makino, Hiroshi ; Mutoh, Shin'ichiro ; Miyama, Masayuki ; Matsuda, Yoshio
概要:
A 64-kb SRAM circuit with a single bit line (BL) for reading and with two BLs for writing was designed. Single-BL readin
…
g is achieved by using a left access transistor and a left shared reading port. We designed the cell layout and confirmed that there is no area penalty for producing two word lines in a memory cell. An analysis of butterfly plots clearly confirms that the single-BL SRAM has the larger static noise margin than the two-BL one. It is confirmed that the static noise margin in the single-BL SRAM is further increased when the BL is precharged to not VDD but to the lower value in the range of VDD/2 to 3VDD/4. In addition, a new sense amplifier circuit without reference voltage is proposed for single-BL reading. We also propose a divided word line architecture for writing to maintain the static noise margin for unwritten blocks. © 2011 IEEE.
続きを見る
|
||||
| 2.
論文 |
論文
|
Nakata, Shunji ; Makino, Hiroshi ; Mutoh, Shin'ichiro ; Miyama, Masayuki ; Matsuda, Yoshio
概要:
Adiabatic charging of a capacitor with a step down converter by changing the duty ratio is considered. First, for a prof
…
ound understanding of the circuit, the general analytical solution of step down converter is considered. It is confirmed that the system can be resolved analytically and that the equilibrium state of current and voltage are consistent with SPICE simulation. Next, adiabatic charging by changing the duty ratio is investigated. From SPICE simulation, it is confirmed that energy dissipation is reduced to one-fourth when four-step charging is used. By increasing the step number, energy dissipation decreases to zero and dissipationless operation is achieved. Adiabatic charging of a capacitor with a step down converter by changing the duty ratio is considered. First, for a profound understanding of the circuit, the general analytical solution of step down converter is considered. It is confirmed that the system can be resolved analytically and that the equilibrium state of current and voltage are consistent with SPICE simulation. Next, adiabatic charging by changing the duty ratio is investigated. From SPICE simulation, it is confirmed that energy dissipation is reduced to one-fourth when four-step charging is used. By increasing the step number, energy dissipation decreases to zero and dissipationless operation is achieved. © 2011 IEEE.
続きを見る
|
||||
| 3.
論文 |
論文
|
Nakata, Shunji ; Maeda, Ryoji ; Kawae, Takeshi ; Morimoto, Akiharu ; Shimizu, Tatsuo
概要:
A thin-film structure comprising Al2O3/Al-rich Al2O3/SiO2 was fabricated on Si substrate. We used radio-frequency magnet
…
ron co-sputtering with Al metal plates set on an Al2O3 target to fabricate the Al-rich Al2O 3 thin film, which is used as a charge storage layer for nonvolatile Al2O3 memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. For a fabricated Al-O capacitor structure, we clarified experimentally that the maximum capacitance in the C-V hysteresis agrees well with the series capacitance of insulators and that the minimum capacitance agrees well with the series capacitance of the semiconductor depletion layer and stacked insulator. When the Al content in the Al-rich Al2O3 is increased, a large charge trap density is obtained. When the Al content in the Al-O is changed from 40 to 58%, the charge trap density increases from 0 to 18 × 1018 cm-3, which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for low-cost nonvolatile memory. © 2011 Elsevier B.V. All rights reserved.
続きを見る
|
||||
| 4.
論文 |
論文
|
Makino, Hiroshi ; Nakata, Shunji ; Suzuki, Hirotsugu ; Morimura, Hiroki ; Mutoh, Shin'ichiro ; Miyama, Masayuki ; Yoshimura, Tsutomu ; Iwade, Shuhei ; Matsuda, Yoshio
概要:
An accelerated evaluation method for the SRAM cell write margin is proposed based on the conventional Write Noise Margin
…
(WNM) definition. The WNM is measured under a lower word line voltage than the power supply voltage VDD. A lower word line voltage is used because the access transistor operates in the saturation mode over a wide range of threshold voltage variation. The final WNM at the VDD word line voltage, the Accelerated Write Noise Margin (AWNM), is obtained by shifting the measured WNM at the lower word line voltage. The amount of WNM shift is determined from the WNM dependence on the word line voltage. As a result, the cumulative frequency of the AWNM displays a normal distribution. A normal distribution of the AWNM drastically improves development efficiency, because the write failure probability can be estimated by a small number of samples. Effectiveness of the proposed method is verified using the Monte Carlo simulation. © 2011 IEEE.
続きを見る
|
||||
| 5.
論文 |
論文
|
Nakata, Shunji ; Kato, Takashi ; Ozaki, Shinya ; Kawae, Takeshi ; Morimoto, Akiharu
概要:
Thin film Al2O3/Al-rich Al2O 3/SiO2 structures were fabricated on p-Si substrates. Radio-frequency magnetron co-sputteri
…
ng was used to form Al-rich Al 2O3 thin film as the charge-trapping layer of nonvolatile Al2O3 memory. Capacitance-voltage measurements showed a large hysteresis due to charge trapping in the Al-rich Al2O 3 layer. The charge trap density was estimated to be 42.7 × 1018 cm- 3, which is the largest value ever reported for an Al-rich Al2O3 layer; it is six times larger than that of a conventional metal-nitride-oxide-silicon memory. Thermal annealing was found to reduce the leakage current of the Al2O3 blocking layer, thereby providing this structure with better data retention at room temperature than an as-deposited one. In addition, the annealed structure was found to exhibit good data retention even at 100 C. © 2013 Elsevier B.V. All rights reserved.
続きを見る
|
||||
| 6.
論文 |
論文
|
Makino, Hiroshi ; Kusumoto, Takahito ; Nakata, Shunji ; Mutoh, Shinichiro ; Miyama, Masayuki ; Yoshimura, Tsutomu ; Iwade, Shuhei ; Matsuda, Yoshio
概要:
金沢大学理工研究域電子情報学系<br />The SRAM operating margin in 65nm technology is analyzed. The peak characteristic in the read margi
…
n versus the supply voltage was found to be caused by the channel length modulation effect. Controlling the memory cell virtual ground line proved to be effective in enlarging the operating margin simultaneously in the read and the write operations. A simple o ptimum circuit which does not require any dynamic voltage c ontrol is proposed, realizing an improvement in the operating m argin comparable to conventional circuits requiring dynamic voltage control. © 2010 IEEE.
続きを見る
|
||||
| 7.
論文 |
論文
|
Nakata, Shunji ; Mutoh, Shin'ichiro ; Makino, Hiroshi ; Miyama, Masayuki ; Matsuda, Yoshio
概要:
金沢大学理工研究域電子情報学系<br />We discuss the stability of an adiabatic stepwise-charging circuit with advanced series capacitors,
…
which is effective for the reduction of the applied voltage to each capacitor. SPICE simulation shows that this circuit is stable even if the initial voltages are lower than zero. For the analytical discussion, we derive a matrix that connects charge and voltage in the circuit and show that the matrix is a positive-definite symmetric one. Therefore, the step voltage is generated spontaneously. We also derive energy dissipation analytically using tank capacitor voltage. Using this formula and SPICE simulation, we clarify that energy dissipation decreases monotonically as a function of time and finally reaches the minimum value. © IEICE 2010.
続きを見る
|
